High-Level Data Link Control (HDLC)

The HDLC module provides a software based HDLC engine that performs bit-oriented protocol manipulation on the host processor. The technique uses a fast tabular lookup to simulatenously traverse 7 or 8 states of the HDLC state machine and perform 16-bit CCITT CRC calculations.

This project provides a module that can be pushed over a Channel Interface (CHI) stream and provides a Communications Device Interface (cdi(7)) that is suitable for linking under LAPD, LAPF, LAPB, V5.2, GR-303, and DPNSS/DASS Data Link multiplexing drivers.

A Soft-HDLC engine is part of recent driver code for SS7 signalling links. This is a version of the Soft-HDLC engine for use by ISDN and ISDN-related signalling components that use normal HDLC (multiple flags between frames, no FISU/LSSU compression or repetition).

This project is in the Testing stage.

This project depends on the Channel Interface (CHI) to the X400P-SS7 and X100P-SS7 drivers.

The design is identical to the SDT Soft-HDLC design with the exception that FISU/LSSU compression/repetition has been removed and multiple flags are placed between frames. Also, the Soft-HDLC engine idles flags instead of FISUs.

A manual page for the HDLC driver can be found here: hdlc(4).

Test programs and results are not yet publicly available. When tests results are available, conformance test results will be available here, and performance test results will be available here.

References for the HDLC project can be found here.

Code for the Soft-HDLC driver can be found in the hdlc and cd sub-directories of the strss7 CVS archive code.

The Soft-HDLC driver will be part of the next major release (0.8.4) of the strss7 package.